WHAT IS INTERFACING ?
Interface is
the path for communication between two components. Interfacing is of two types,
memory interfacing and I/O interfacing.
Memory Interfacing
When we are
executing any instruction, we need the microprocessor to access the memory for
reading instruction codes and the data stored in the memory. For this, both the
memory and the microprocessor requires some signals to read from and write to
registers.
The interfacing
process includes some key factors to match with the memory requirements and
microprocessor signals. The interfacing circuit therefore should be designed in
such a way that it matches the memory signal requirements with the signals of
the microprocessor.
IO Interfacing
There are various
communication devices like the keyboard, mouse, printer, etc. So, we need to
interface the keyboard and other devices with the microprocessor by using
latches and buffers. This type of interfacing is known as I/O interfacing.
Block Diagram of Memory
and I/O Interfacing
8085 Interfacing Pins
Following is the
list of 8085 pins used for interfacing with other devices −
A15 - A8 (Higher Address
Bus)
AD7 - AD0(Lower Address/Data Bus)
ALE
RD
WR
READY
Ways of Communication −
Microprocessor with the Outside World?
There are two ways
of communication in which the microprocessor can connect with the outside
world.
Serial Communication Interface
Parallel Communication interface
Serial
Communication Interface − In this type of communication, the interface
gets a single byte of data from the microprocessor and sends it bit by bit to the
other system serially and vice-a-versa.
Parallel
Communication Interface − In this type of communication, the interface
gets a byte of data from the microprocessor and sends it bit by bit to the
other systems in simultaneous (or) parallel fashion and vice-a-versa.
8279 - Programmable
Keyboard
8279 programmable keyboard/display controller is designed by Intel that
interfaces a keyboard with the CPU. The keyboard first scans the keyboard and
identifies if any key has been pressed. It then sends their relative response
of the pressed key to the CPU and vice-a-versa.
How Many Ways the Keyboard
is Interfaced with the CPU?
The Keyboard can be interfaced either in the interrupt or the polled mode.
In the Interrupt mode, the processor is requested service only if any key
is pressed, otherwise the CPU will continue with its main task.
In the Polled mode, the CPU periodically reads an internal flag of
8279 to check whether any key is pressed or not with key pressure.
How Does 8279 Keyboard
Work?
The keyboard consists of maximum 64 keys, which are interfaced with the CPU
by using the key-codes. These key-codes are de-bounced and stored in an 8-byte
FIFORAM, which can be accessed by the CPU. If more than 8 characters are
entered in the FIFO, then it means more than eight keys are pressed at a time.
This is when the overrun status is set.
If a FIFO contains a valid key entry, then the CPU is interrupted in an
interrupt mode else the CPU checks the status in polling to read the entry.
Once the CPU reads a key entry, then FIFO is updated, and the key entry is pushed
out of the FIFO to generate space for new entries.
Architecture and
Description
I/O Control and Data Buffer
This unit controls the flow of data through the microprocessor. It is
enabled only when D is low. Its data buffer interfaces the external bus of the
system with the internal bus of the microprocessor. The pins A0, RD, and WR are
used for command, status or data read/write operations.
Control and Timing Register
and Timing Control
This unit contains registers to store the keyboard, display modes, and
other operations as programmed by the CPU. The timing and control unit handles
the timings for the operation of the circuit.
Scan Counter
It has two modes i.e. Encoded mode and Decoded mode. In the
encoded mode, the counter provides the binary count that is to be externally
decoded to provide the scan lines for the keyboard and display.
In the decoded scan mode, the counter internally decodes the least
significant 2 bits and provides a decoded 1 out of 4 scan on SL0-SL3.
Return Buffers, Keyboard
Debounce, and Control
This unit first scans the key closure row-wise, if found then the keyboard
debounce unit debounces the key entry. In case, the same key is detected, then
the code of that key is directly transferred to the sensor RAM along with SHIFT
& CONTROL key status.
FIFO/Sensor RAM and Status
Logic
This unit acts as 8-byte first-in-first-out (FIFO) RAM where the key code
of every pressed key is entered into the RAM as per their sequence. The status
logic generates an interrupt request after each FIFO read operation till the
FIFO gets empty.
In the scanned sensor matrix mode, this unit acts as sensor RAM where its
each row is loaded with the status of their corresponding row of sensors into
the matrix. When the sensor changes its state, the IRQ line changes to high and
interrupts the CPU.
Display Address Registers
and Display RAM
This unit consists of display address registers which holds the addresses
of the word currently read/written by the CPU to/from the display RAM.
8279 − Pin Description
The following figure shows the pin diagram of 8279 −
Data Bus Lines, DB0 - DB7
These are 8 bidirectional data bus lines used to transfer the data to/from
the CPU.
CLK
The clock input is used to generate internal timings required by the
microprocessor.
RESET
As the name suggests this pin is used to reset the microprocessor.
CS Chip Select
When this pin is set to low, it allows read/write operations, else this pin
should be set to high.
A0
This pin indicates the transfer of command/status information. When it is
low, it indicates the transfer of data.
RD, WR
This Read/Write pin enables the data buffer to send/receive data over the
data bus.
IRQ
This interrupt output line goes high when there is data in the FIFO sensor
RAM. The interrupt line goes low with each FIFO RAM read operation. However, if
the FIFO RAM further contains any key-code entry to be read by the CPU, this
pin again goes high to generate an interrupt to the CPU.
Vss,
Vcc
These are the ground and power supply lines of the microprocessor.
SL0 −
SL3
These are the scan lines used to scan the keyboard matrix and display the
digits. These lines can be programmed as encoded or decoded, using the mode
control register.
RL0 −
RL7
These are the Return Lines which are connected to one terminal of keys,
while the other terminal of the keys is connected to the decoded scan lines.
These lines are set to 0 when any key is pressed.
SHIFT
The Shift input line status is stored along with every key code in FIFO in
the scanned keyboard mode. Till it is pulled low with a key closure, it is
pulled up internally to keep it high
CNTL/STB - CONTROL/STROBED
I/P Mode
In the keyboard mode, this line is used as a control input and stored in
FIFO on a key closure. The line is a strobe line that enters the data into FIFO
RAM, in the strobed input mode. It has an internal pull up. The line is pulled
down with a key closure.
BD
It stands for blank display. It is used to blank the display during digit
switching.
OUTA0 –
OUTA3 and OUTB0 – OUTB3
These are the output ports for two 16x4 or one 16x8 internal display
refresh registers. The data from these lines is synchronized with the scan
lines to scan the display and the keyboard.
Operational Modes of 8279
There are two modes of operation on 8279 − Input Mode and Output
Mode.
Input Mode
This mode deals with the input given by the keyboard and this mode is
further classified into 3 modes.
Scanned Keyboard Mode −
In this mode, the key matrix can be interfaced using either encoded or decoded
scans. In the encoded scan, an 8×8 keyboard or in the decoded scan, a 4×8
keyboard can be interfaced. The code of key pressed with SHIFT and CONTROL
status is stored into the FIFO RAM.
Scanned Sensor Matrix −
In this mode, a sensor array can be interfaced with the processor using either
encoder or decoder scans. In the encoder scan, 8×8 sensor matrix or with
decoder scan 4×8 sensor matrix can be interfaced.
Strobed Input − In this
mode, when the control line is set to 0, the data on the return lines is stored
in the FIFO byte by byte.
Output Mode
This mode deals with display-related operations. This mode is further
classified into two output modes.
Display Scan − This
mode allows 8/16 character multiplexed displays to be organized as dual
4-bit/single 8-bit display units.
Display Entry − This
mode allows the data to be entered for display either from the right side/left
side.
Microprocessor - 8257 DMA
Controller
DMA stands for Direct Memory Access. It is designed by Intel to transfer
data at the fastest rate. It allows the device to transfer the data directly
to/from memory without any interference of the CPU.
Using a DMA controller, the device requests the CPU to hold its data,
address and control bus, so the device is free to transfer data directly
to/from the memory. The DMA data transfer is initiated only after receiving
HLDA signal from the CPU.
How DMA Operations are Performed?
Following is the sequence of operations performed by a DMA −
Initially, when any device
has to send data between the device and the memory, the device has to send DMA
request (DRQ) to DMA controller.
The DMA controller sends
Hold request (HRQ) to the CPU and waits for the CPU to assert the HLDA.
Then the microprocessor
tri-states all the data bus, address bus, and control bus. The CPU leaves the
control over bus and acknowledges the HOLD request through HLDA signal.
Now the CPU is in HOLD
state and the DMA controller has to manage the operations over buses between
the CPU, memory, and I/O devices.
Features of 8257
Here is a list of some of the prominent features of 8257 −
It has four channels which
can be used over four I/O devices.
Each channel has 16-bit
address and 14-bit counter.
Each channel can transfer
data up to 64kb.
Each channel can be
programmed independently.
Each channel can perform
read transfer, write transfer and verify transfer operations.
It generates MARK signal to
the peripheral device that 128 bytes have been transferred.
It requires a single phase
clock.
Its frequency ranges from
250Hz to 3MHz.
It operates in 2 modes,
i.e., Master mode and Slave mode.
8257 Architecture
The following image shows the architecture of 8257 −
8257 Pin Description
The following image shows the pin diagram of a 8257 DMA controller −
DRQ0−DRQ3
These are the four individual channel DMA request inputs, which are used by
the peripheral devices for using DMA services. When the fixed priority mode is
selected, then DRQ0 has the
highest priority and DRQ3 has
the lowest priority among them.
DACKo −
DACK3
These are the active-low DMA acknowledge lines, which updates the
requesting peripheral about the status of their request by the CPU. These lines
can also act as strobe lines for the requesting devices.
Do −
D7
These are bidirectional, data lines which are used to interface the system
bus with the internal data bus of DMA controller. In the Slave mode, it carries
command words to 8257 and status word from 8257. In the master mode, these
lines are used to send higher byte of the generated address to the latch. This
address is further latched using ADSTB signal.
IOR
It is an active-low bidirectional tri-state input line, which is used by the
CPU to read internal registers of 8257 in the Slave mode. In the master mode,
it is used to read data from the peripheral devices during a memory write
cycle.
IOW
It is an active low bi-direction tri-state line, which is used to load the
contents of the data bus to the 8-bit mode register or upper/lower byte of a
16-bit DMA address register or terminal count register. In the master mode, it
is used to load the data to the peripheral devices during DMA memory read
cycle.
CLK
It is a clock frequency signal which is required for the internal operation
of 8257.
RESET
This signal is used to RESET the DMA controller by disabling all the DMA
channels.
Ao -
A3
These are the four least significant address lines. In the slave mode, they
act as an input, which selects one of the registers to be read or written. In
the master mode, they are the four least significant memory address output
lines generated by 8257.
CS
It is an active-low chip select line. In the Slave mode, it enables the
read/write operations to/from 8257. In the master mode, it disables the
read/write operations to/from 8257.
A4 -
A7
These are the higher nibble of the lower byte address generated by DMA in
the master mode.
READY
It is an active-high asynchronous input signal, which makes DMA ready by
inserting wait states.
HRQ
This signal is used to receive the hold request signal from the output
device. In the slave mode, it is connected with a DRQ input line 8257. In
Master mode, it is connected with HOLD input of the CPU.
HLDA
It is the hold acknowledgement signal which indicates the DMA controller
that the bus has been granted to the requesting peripheral by the CPU when it
is set to 1.
MEMR
It is the low memory read signal, which is used to read the data from the
addressed memory locations during DMA read cycles.
MEMW
It is the active-low three state signal which is used to write the data to
the addressed memory location during DMA write operation.
ADST
This signal is used to convert the higher byte of the memory address
generated by the DMA controller into the latches.
AEN
This signal is used to disable the address bus/data bus.
TC
It stands for ‘Terminal Count’, which indicates the present DMA cycle to
the present peripheral devices.
MARK
The mark will be activated after each 128 cycles or integral multiples of
it from the beginning. It indicates the current DMA cycle is the 128th cycle
since the previous MARK output to the selected peripheral device.
Vcc
It is the power signal which is required for the operation of the circuit.
Microcontrollers -
Overview
A microcontroller is a small and low-cost microcomputer, which is
designed to perform the specific tasks of embedded systems like displaying
microwave’s information, receiving remote signals, etc.
The general microcontroller consists of the processor, the memory (RAM,
ROM, EPROM), Serial ports, peripherals (timers, counters), etc.
Difference between Microprocessor and Microcontroller
The following table highlights the differences between a microprocessor and
a microcontroller −
Microcontroller
|
Microprocessor
|
Microcontrollers
are used to execute a single task within an application.
|
Microprocessors
are used for big applications.
|
Its
designing and hardware cost is low.
|
Its
designing and hardware cost is high.
|
Easy to
replace.
|
Not so easy
to replace.
|
It is built
with CMOS technology, which requires less power to operate.
|
Its power
consumption is high because it has to control the entire system.
|
It consists
of CPU, RAM, ROM, I/O ports.
|
It doesn’t
consist of RAM, ROM, I/O ports. It uses its pins to interface to peripheral
devices.
|
Types of Microcontrollers
Microcontrollers are divided into various categories based on memory,
architecture, bits and instruction sets. Following is the list of their types −
Bit
Based on bit configuration, the microcontroller is further divided into
three categories.
8-bit microcontroller −
This type of microcontroller is used to execute arithmetic and logical
operations like addition, subtraction, multiplication division, etc. For
example, Intel 8031 and 8051 are 8 bits microcontroller.
16-bit microcontroller −
This type of microcontroller is used to perform arithmetic and logical
operations where higher accuracy and performance is required. For example,
Intel 8096 is a 16-bit microcontroller.
32-bit microcontroller −
This type of microcontroller is generally used in automatically controlled
appliances like automatic operational machines, medical appliances, etc.
Memory
Based on the memory configuration, the microcontroller is further divided
into two categories.
External memory
microcontroller − This type of microcontroller is designed in such a way
that they do not have a program memory on the chip. Hence, it is named as
external memory microcontroller. For example: Intel 8031 microcontroller.
Embedded memory
microcontroller − This type of microcontroller is designed in such a way
that the microcontroller has all programs and data memory, counters and timers,
interrupts, I/O ports are embedded on the chip. For example: Intel 8051
microcontroller.
Instruction Set
Based on the instruction set configuration, the microcontroller is further
divided into two categories.
CISC − CISC stands for
complex instruction set computer. It allows the user to insert a single
instruction as an alternative to many simple instructions.
RISC − RISC stands for
Reduced Instruction Set Computers. It reduces the operational time by
shortening the clock cycle per instruction.
Applications of Microcontrollers
Microcontrollers are widely used in various different devices such as −
Light sensing and
controlling devices like LED.
Temperature sensing and
controlling devices like microwave oven, chimneys.
Fire detection and safety
devices like Fire alarm.
Measuring devices like Volt Meter
.DMA Controllerनियंत्रक को प्रोसेसर बोर्ड में एकीकृत किया जाता है और सभी डीएमए डेटा स्थानान्तरण का प्रबंधन करता है। सिस्टम मेमोरी और 110 डिवाइस के बीच डेटा ट्रांसफ़र करना दो चरण की आवश्यकता है। डाटा भेजने वाले डिवाइस से डीएमए कंट्रोलर तक और तब प्राप्त डिवाइस पर जाता है। माइक्रोप्रोसेसर डीएमए कंट्रोलर को स्थान, गंतव्य, और स्थानांतरित करने वाले डेटा की मात्रा देता है। फिर डीएमए नियंत्रक डेटा को स्थानांतरित करता है, जो माइक्रोप्रोसेसर को अन्य प्रोसेसिंग कार्यों के साथ जारी रखने की इजाजत देता है। जब एक डिवाइस को डेटा भेजने या प्राप्त करने के लिए माइक्रो चैनल बस का उपयोग करने की आवश्यकता होती है, तो यह उन सभी अन्य उपकरणों के साथ प्रतिस्पर्धा करती है जो बस के नियंत्रण पाने की कोशिश कर रहे हैं। इस प्रक्रिया को मध्यस्थता के रूप में जाना जाता है डीएमए नियंत्रक इसके बजाय बस के नियंत्रण के लिए मध्यस्थता नहीं करता है; I / O उपकरण जो डेटा भेज रहा है या प्राप्त कर रहा है (डीएमए स्लेव) मध्यस्थता में भाग लेता है। यह डीएमए कंट्रोलर है, हालांकि, जब केंद्रीय मध्यस्थता नियंत्रण बिंदु डीएमए दास के अनुरोध को अनुदान देता है तो बस उस पर नियंत्रण रखता है।
What is 8257
DMA controller?
8257 DMA stands for 4-channel Direct Memory Access. It is
specially designed by Intel for data transfer at the highest speed. Its initial
function is to generate a peripheral request which allows the device to
transfer the data directly to/from memory without any interference of the CPU.
With the use of a DMA controller, the device sends requests to the
CPU to hold its data, sequential memory address and control bus, which helps
the device to transfer data directly to/from the memory. The DMA data transfer
is initiated only after receiving HLDA signal from the CPU.
Features of
8257
Here is a list of some of the prominent features of 8257 −
·
It has four channels which can be exhibited over four I/O devices.
·
Each channel has 16-bit address and 14-bit counter.
·
Data transfer of each channel can be taken up to 64kb.
·
Each channel can be programmed independently.
·
Each channel can perform certain specific actions i.e, read
transfer, write transfer and verify transfer operations.
·
It produces MARK signal to the peripheral device that 128 bytes
have been transferred.
·
It requires a single phase clock.
·
Its frequency ranges from 250Hz to 3MHz.
·
It performs operations in 2 modes, i.e., Master mode and Slave
mode.
8257
Architecture
The following image shows the architecture of 8257 −
DRQ0−DRQ3
As seen in the above diagram these are the four individual
asynchronous channel DMA request inputs, which are used by the peripheral
devices to obtain DMA services. When the rotating priority mode is selected,
then DRQ0 will get the highest priority and DRQ3 will get the lowest priority
among them.
DACKo − DACK3
These
are the active-low and high (inactive)DMA acknowledge lines, which updates the
peripheral requesting device service about the status of their request by the
CPU. These lines can also act as strobe lines for the requesting devices.
Do − D7
These are bidirectional, data lines which help to interface the
system bus with the internal data bus of DMA controller. In the Slave mode,
command words are carried to 8257 and status words from 8257. In the master
mode, the lines which are used to send higher byte of the generated address are
sent to the latch. This address is further latched using ADSTB signal.
IOR
It is an active-low bidirectional tri-state input line, which
helps to read the internal registers of 8257 by the CPU in the Slave mode. In
the master mode, it also helps in reading the data from the peripheral devices
during a memory write cycle.
IOW
It is an active low bi-direction tri-state line, which helps in
loading the contents of the data bus to the 8-bit mode register or upper/lower
byte of a 16-bit DMA address register or terminal count register. In the master
mode, it is used to load the data to the peripheral devices during DMA memory
read cycle.
CLK
It is a clock frequency signal which is required to perform
internal operation of 8257.
RESET
This signal is used to RESET the DMA controller by disabling all
the DMA channels.
Ao - A3
These are the four least significant address lines. In the slave
mode, they perform as an input, which selects one of the registers to be read
or written. In the master mode, they are the outputs which contain four least
significant memory address output lines produced by 8257.
CS
It is an active-low chip select line. In the Slave mode, it
enables the read/write operations to/from 8257. In the master mode, it
automatically disables the read/write operations to/from 8257.
A4 - A7
These are the higher nibble of the lower byte address generated by
DMA in the master mode.
READY
It is an active-high asynchronous input signal, which helps DMA to
make ready by inserting wait states.
HRQ
This signal helps to receive the hold request signal sent from the
output device. In the slave mode, it is connected with a DRQ input line 8257.
In Master mode, it is connected with HOLD input of the CPU.
HLDA
It is the hold acknowledgement signal which indicates the DMA
controller that the bus has been granted to the requesting peripheral by the
CPU when it is set to 1.
MEMR
It is the low memory read signal, which is used to read the data
from the addressed memory locations during DMA read cycles.
MEMW
It is the active-low three state signal which is used to write the
data to the addressed memory location during DMA write operation.
ADST
This signal is used to convert the higher byte of the memory
address generated by the DMA controller into the latches.
AEN
This signal is used to disable the address bus/data bus.
TC
It stands for ‘Terminal Count’, which indicates the present DMA
cycle to the present peripheral devices.
MARK
The mark will be activated after each 128 cycles or integral
multiples of it from the beginning. It indicates the current DMA cycle is the
128th cycle since the previous MARK output to the selected peripheral device.
Vcc
It is the power signal which is required for the operation of the
circuit.
Good
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