Difference between Debugger and Linker ?

 Debugger: As its name suggests the debugger is used to test and debug programs. The debugger allows a user to test a program step by step, so that the problem points or steps can be identified and rectified. It allows the user to inspect the registers and the memory locations after a program has executed.

Assembler: The assembler is used to convert assembly language written by a user or a program into a machine recognizable format.

- Linker: There are certain programs which are large in size and cannot be executed at one go simultaneously. Such programs are divided into subprograms also known as modules. The linker is used to link such small programs to form one large program.

Briefly explain DMA and its various addressing modes.

- The DMA or the direct memory access is a type of process in which the System bus control is accessed and controlled by an external device in place of the CPU.

- It is primarily used for the high speed transfer of data from mass storage devices.

- The DMA functions by directly transferring data to and from from the memory to the devices.

- The various modes of operation of the DMA are as follows: Demand mode, Single mode, Block mode and Cascade mode. 

- The characteristic of the demand mode is that it can transfer data until the Dreq input becomes inactive.

Microprocessor

A Microprocessor is an important part of a computer architecture without which you be able to perform any thing on your computer system. It is a programmable device that takes in input perform some arithmetic and logical operations over it and produce desired output. In simple words, a Microprocessor is a digital device on a chip which can fetch instruction from memory, decode and execute them and give results.

Basics of Microprocessor –

A Microprocessor takes a bunch of instructions in machine language and executes them, telling the processor what it has to do. Microprocessor performs three basic things while executing the instruction:

1.    It performs some basic operations like addition, subtraction, multiplication, division and some logical operations using its Arithmetic and Logical Unit (ALU). New Microprocessors also perform operations on floating point numbers also.

2.    Data in Microprocessor can move from one location to another.

3.    It has a Program Counter (PC) register that stores the address of next instruction based on the value of PC, Microprocessor jumps from one location to another and takes decision.

Microprocessor | 8251 USART

8251 universal synchronous asynchronous receiver transmitter (USART) acts as a mediator between microprocessor and peripheral to transmit serial data into parallel form and vice versa.

1.       It takes data serially from peripheral (outside devices) and converts into parallel data.

2.       After converting the data into parallel form, it transmits it to the CPU.

3.       Similarly, it receives parallel data from microprocessor and converts it into serial form.

4.       After converting data into serial form, it transmits it to outside device (peripheral).

Block Diagram of 8251 USART –

It contains the following blocks:

Data bus buffer –

This block helps in interfacing the internal data bus of 8251 to the system data bus. The data transmission is possible between 8251 and CPU by the data bus buffer block.

8259 PIC Microprocessor

8259 microprocessor is defined as Programmable Interrupt Controller (PIC)microprocessor. There are 5 hardware interrupts and 2 hardware interrupts in 8085 and 8086 respectively. But by connecting 8259 with CPU, we can increase the interrupt handling capability. 8259 combines the multi interrupt input sources into a single interrupt output. Interfacing of single PIC provides 8 interrupts inputs from IR0-IR7.

For example, Interfacing of 8085 and 8259 increases the interrupt handling capability of 8085 microprocessor from 5 to 8 interrupt levels.

Features of 8259 PIC microprocessor –

1.    Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor.

2.    It can be programmed either in level triggered or in edge triggered interrupt level.

3.    We can masked individual bits of interrupt request register.

4.    We can increase interrupt handling capability upto 64 interrupt level by cascading further 8259 PIC.

5.    Clock cycle is not required.

The Block Diagram consists of 8 blocks which are – Data Bus Buffer, Read/Write Logic, Cascade Buffer Comparator, Control Logic, Priority Resolver and 3 registers- ISR, IRR, IMR.

1.    Data bus buffer –
This Block is used as a mediator between 8259 and 8085/8086 microprocessor by acting as a buffer. It takes the control word from the 8085 (let say) microprocessor and transfer it to the control logic of 8259 microprocessor. Also, after selection of Interrupt by 8259 microprocessor, it transfer the opcode of the selected Interrupt and address of the Interrupt service sub routine to the other connected microprocessor. The data bus buffer consists of 8 bits represented as D0-D7 in the block diagram. Thus, shows that a maximum of 8 bits data can be transferred at a time.

2.    Read/Write logic –
This block works only when the value of pin CS is low (as this pin is active low). This block is responsible for the flow of data depending upon the inputs of RD and WR. These two pins are active low pins used for read and write operations.

3.    Control logic –
It is the centre of the microprocessor and controls the functioning of every block. It has pin INTR which is connected with other microprocessor for taking interrupt request and pin INT for giving the output. If 8259 is enabled, and the other microprocessor Interrupt flag is high then this causes the value of the output INT pin high and in this way 8259 responds to the request made by other microprocessor.

4.    Interrupt request register (IRR) –
It stores all the interrupt level which are requesting for Interrupt services.

5.    Interrupt service register (ISR) –
It stores the interrupt level which are currently being executed.

6.    Interrupt mask register (IMR) –
It stores the interrupt level which have to be masked by storing the masking bits of the interrupt level.

7.    Priority resolver –
It examines all the three registers and set the priority of interrupts and according to the priority of the interrupts, interrupt with highest priority is set in ISR register. Also, it reset the interrupt level which is already been serviced in IRR.

8.    Cascade buffer –
To increase the Interrupt handling capability, we can further cascade more number of pins by using cascade buffer. So, during increment of interrupt capability, CSA lines are used to control multiple interrupt structure.

Interrupts in 8086 microprocessor

An interrupt is a condition that halts the microprocessor temporarily to work on a different task and then return to its previous task. Interrupt is an event or signal that request to attention of CPU. This halt allows peripheral devices to access the microprocessor.

Whenever an interrupt occurs the processor completes the execution of the current instruction and starts the execution of an Interrupt Service Routine (ISR) or Interrupt Handler. ISR is a program that tells the processor what to do when the interrupt occurs. After the execution of ISR, control returns back to the main routine where it was interrupted.

In 8086 microprocessor following tasks are performed when microprocessor encounters an interrupt:

1.    The value of flag register is pushed into the stack. It means that first the value of SP (Stack Pointer) is decremented by 2 then the value of flag register is pushed to the memory address of stack segment.

2.    The value of starting memory address of CS (Code Segment) is pushed into the stack.

3.    The value of IP (Instruction Pointer) is pushed into the stack.

4.    IP is loaded from word location (Interrupt type) * 04.

5.    CS is loaded from the next word location.

6.    Interrupt and Trap flag are reset to 0.

The different types of interrupts present in 8086 microprocessor are given by:

1.    Hardware Interrupts –

Hardware interrupts are those interrupts which are caused by any peripheral device by sending a signal through a specified pin to the microprocessor. There are two hardware interrupts in 8086 microprocessor. They are:

·         (A) NMI (Non Maskable Interrupt) – It is a single pin non maskable hardware interrupt which cannot be disabled. It is the highest priority interrupt in 8086 microprocessor. After its execution, this interrupt generates a TYPE 2 interrupt. IP is loaded from word location 00008 H and CS is loaded from the word location 0000A H.

·         (B) INTR (Interrupt Request) – It provides a single interrupt request and is activated by I/O port. This interrupt can be masked or delayed. It is a level triggered interrupt. It can receive any interrupt type, so the value of IP and CS will change on the interrupt type received.

2.    Software Interrupts – These are instructions that are inserted within the program to generate interrupts. There are 256 software interrupts in 8086 microprocessor. The instructions are of the format INT type where type ranges from 00 to FF. The starting address ranges from 00000 H to 003FF H. These are 2 byte instructions. IP is loaded from type * 04 H and CS is loaded from the next address give by (type * 04) + 02 H. Some important software interrupts are:

·         (A) TYPE 0 corresponds to division by zero(0).

·         (B) TYPE 1 is used for single step execution for debugging of program.

·         (C) TYPE 2 represents NMI and is used in power failure conditions.

·         (D) TYPE 3 represents a break-point interrupt.

·         (E) TYPE 4 is the overflow interrupt.